On-die clock trees, such as those that are integrated onto the die of an integrated circuit, consume a significant amount of power. Power consumption has become a very important concern in integrated circuit design considerations. Thus, saving power consumption on the clock tree is one area of that modern integrated circuit designs can benefit from.
Normally, a standard CMOS (complementary metal-oxide semiconductor) clock tree is extended out to a number of clock tree drop off points that each consist of the end of a branch of the tree. The tree is uniformly distributed with drivers (i.e. buffers) to drive the clock signal equally across the tree to all drop off points. Each driver introduces a certain amount of noise (i.e. jitter) into the clock signal. As the clock signal travels through more drivers in a deep clock tree, the jitter within the signal is increased.
The drivers are each supplied with a certain amount of power (i.e. a specific voltage level that causes them to consume a specific amount of power). For each driver, as the supplied power is increased, the gain of the driver is increased. As gain increases, signal jitter decreases. Thus, to compensate for the signal jitter introduced by the many drivers in a large clock tree, the power supplied to all of the drivers in the tree can be increased. Therefore, if a circuit requires a clock signal with little jitter, supplying the clock tree drivers with high power will help. Alternatively, if the circuit does not have strict requirements on the preciseness of the clock signal, the clock tree drivers may be supplied with less power, which would save on power consumption but would cause greater jitter in the clock signal.
Current clock trees are uniformly distributed to all drop off points, although this sometimes requires unnecessary power consumption because different circuitry beyond the different drop off points do not necessarily require the same level of precision (i.e. lack of jitter) of the clock signal.
Apart from CMOS drivers, there are other types of high-performance drivers that can be utilized in clock trees, such as common mode logic (CML) drivers. The performance of a driver is at least partially a function of the speed at which the driver can switch from outputting the clock signal at a low voltage to a high voltage and vice versa. The implementation of a clock tree balances a number of important factors. For example, a standard CMOS driver clock tree generally has a low cost associated with its implementation because CMOS drivers are simple and very standard circuits. The CMOS driver clock tree also generally consumes less power per driver than a high-performance clock tree. On the other hand, a CML (or other high-performance) driver clock tree generally introduces less jitter and less clock skew to the driven clock signal than a CMOS driver clock tree. Thus, tradeoffs exist when deciding whether to implement a lower or higher performance clock tree.